ahb-lite-usb-verification | Akshath Raghav R

This project implements the handling of USB bulk transfers between a host (managing device) and an endpoint (System on Chip, or SoC), utilizing the AHB-Lite bus interface for communication. The design consists of several modules to manage USB data reception, transmission, buffering, and communication with the internal bus using AHB-Lite.

All files for this project can be found here. This project was completed as a part of ECE 337, and requires that code be private – Please reach out if you’d like to view it, and are not taking the course.

Overview

This design handles the reception and transmission of USB bulk transfer packets between a host and a device endpoint. The data transfer is managed by four main modules:

USB RX - Receives and validates packets from the host to the endpoint.
USB TX - Sends packets from the endpoint to the host.
Data Buffer - Buffers the data for incoming and outgoing transfers.
AHB-Lite Satellite - Communicates with the internal bus using the AHB-Lite protocol.

Additionally, the design supports the AHB-Lite bus interface, which facilitates communication between the core and satellite modules.

Team Members

Team members contributing to this project, in alphabetical order, are:

Atharva Bhide (bhide1)
Akshath Raghav Ravikiran (araviki)
Armaan Kanchan (kanchan)

AHB-Lite Bus Interface

Controller Interface

The controller interface is responsible for initiating all requests on the AHB-Lite bus. It sends read and write commands to the bus and manages the routing of signals to the appropriate satellite devices.

Satellite Interface

The satellite interface devices respond to requests directed to them through the AHB-Lite bus. In this design, the AHB-Lite Satellite handles communication with the internal bus, ensuring data is transferred between the core and other system components.

Bus Fabric

The bus fabric is the physical layer of the AHB-Lite bus, handling the routing of signals and data between the controller and satellite devices. It manages the connections between different components of the SoC, enabling communication during AHB-Lite transactions.

Design Architecture

Modules

1. USB RX (Receiver)

The USB RX module handles the reception and validity checking of basic packet types sent from the host to the endpoint. This module works during bulk transfers and ensures that received packets are correctly validated before being passed to the internal data buffer. The RX_Transfer_active signal goes high when the reciever reiceives a sync byte, and is on during the complete data transfer. The RX_packet signal notifies the AHB Satellite of the type of packet being received. Finally, when the receiver gets Data packets, it, first checks if there is enough space in the Data buffer (using the Buffer_Occupancy input signal), and then sends it to the data buffer with a control signal (Store_RX_Packet_Data) instructing it to store the data. Incase of an incorrect packet, or invalid transaction (eg. End of Packet signal received prematurely, or host trying to send in data when the data buffer is full), the RX_Error signal goes high to inform the AHB Satellite. Additionally, the flush signal goes high to flush the data buffer incase of an error.

2. USB TX (Transmitter)

The USB TX module handles the transmission of data packets from the endpoint to the host. It manages the transfer of bulk packets and ensures that data is sent correctly during endpoint-to-host transfers.

The way this module works can be explained in 4 broad parts: 1) FSM: This is a state machine which takes different branches based on the TX_Packet signal and is responsible for all of the control signals such as enable_timer and EOP_en, etc. 2) Timer: This is designed to shift data at 12MHz. It follows an 8/8/9 rollover value mechanism which ensures correct timing. 3) Shift Register: There is an 8 bit pts sr that shifts out the necessary bits into the NRZI encoder. 4) NRZI Encoding: This follows the NRZI encoder toggling DP/DM when it gets a 0 and keeps DP/DM the same when it receives a 1. Further, it ensures that EOP is sent correctly.

3. Data Buffer

The Data Buffer module is responsible for correctly buffering data to be sent or received during bulk transfers. This module:

Buffers the data to be sent during an endpoint-to-host transfer.
Stores the data received from the host during a host-to-endpoint transfer.
Tracks the occupancy of the buffer to ensure smooth data transfer.

4. AHB-Lite Satellite

The AHB-Lite Satellite module handles the functionality specific to the AHB-Lite Satellite Interface. It manages communication between the AHB Bus and internal modules (like Data Buffer and TX modules), overseeing the transfer of data to and from the SoC core. The Controller can request information from the internal registers of the Satellite, which tracks information such as the Packet ID Type received from the RX module. From this, it is possible to also find out if there is any data present to be read in from the data buffer, or if there has been any error during processing from either RX or TX. Using another one of the Satellite’s Internal Registers, the Controller can write specific values which will initiate the sending of a Packet to the TX module. The Controller also has the ability to flush any data which has been read into the Data Buffer. Finally, with the help of the Data Buffer itself, the Satellite has an FSM enabling it to push data written to it (from the Controller) or read data requested from it (from the RX).
Finally, the Satellite is required to protect its internal registers from incorrect addressing and unallowed writes, as well as ensuring the Data Buffer overflow and underflow is taken care of.

Individual RTL Diagrams

RX

TX

Data Buffer (Circular FIFO)

AHB-Satellite

End-to-End Behavior

This section describes the multi-transaction behavior of host-to-endpoint and endpoint-to-host transfers, which defines the high-level flow of operations from the host to the endpoint and vice versa.

Host-to-Endpoint Transfers

The SoC core periodically checks the status register for the arrival of a Host-to-Endpoint Token.
The SoC core verifies that the Data Buffer is empty and ready to receive a data packet.
The SoC core periodically checks the status register to confirm that new data has arrived.
Once data is received, the SoC core issues an ‘ACK’ to the design.
The SoC core checks the buffer occupancy register to determine how much data was received.
The SoC core retrieves the data via a sequence of read operations.
Once all data has been retrieved, the data-available flag in the status register is cleared.

Endpoint-to-Host Transfers

The SoC core verifies that the Data Buffer is empty.
The SoC core writes the data to be sent into the Data Buffer.
When the buffer contains the required amount of data, the SoC core triggers the design to send a data packet.
The SoC core periodically checks the status to ensure the data packet has been sent successfully.
The SoC core checks for an ‘ACK’ from the host and handles any errors if another packet type is received.

Key Requirements

System Clock: The design operates with a system clock rate of 100 MHz.
Data Rate: USB data is transferred at a 12 MHz rate.
Bus Errors: Ensures that bus errors are handled correctly, as per the hresp and hready signals.

Directory Overview

NOTE: Our Top-Level is named “cdl_bus.sv”.

The SystemVerilog modules are defined in the following files:
The Testbenches for the above modules are defined in the following files:
The Waveforms can be accessed by running QuestaSim with the following .do files:
The Report files can be accessed here:
The Synthesis Report file for our top level can be found here:
- synth.log
The Verification plan can be found here:
- cdl_verification_plan.pdf —

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