zicond

The Zicond Extension aims to enhance the RISC-V instruction set architecture by introducing a simplistic pair of conditional instructions. Traditional condition-based operations in RISC-V involve using multiple instructions and branches to evaluate and execute actions, leading to increased code complexity and a higher rate of branch mispredictions. This extension addresses this inefficiency by allowing for register-to-register operations that require a smarter, but reliable, use of register values to negate the use of branches. Furthermore, the current RISC-V core being developed for the upcoming AFTx07 chip tape-out does not have a branch predictor implemented, underscoring the necessity of this project.

The primary objective of this project is to implement and verify the functionality of the Zicond extension within the existing RISC-V architecture. This includes designing the new instructions, integrating them into the core, and creating comprehensive testbenches to ensure correct implementation and performance benefits. By addressing the lack of branch prediction in the current core, this project seeks to significantly improve the robustness of the AFTx07 chip.

You can find the code here and my presentation here.

For Purdue SoCET Students: You can find a guide to working with RISCVBusiness/FuseSoC/Verilator to add extensions here